Intel i3-4020Y CL8064701512402 Data Sheet

SA_RAS#

RAS Control Signal: This signal is used with SA_CAS# and

SA_WE# (along with SA_CS#) to define the SRAM

Commands.

O

SA_CAS#

CAS Control Signal: This signal is used with SA_RAS# and

SA_WE# (along with SA_CS#) to define the SRAM

Commands.

O

SA_DQSP[7:0]
SA_DQSN[7:0]

Data Strobes: SA_DQS[7:0] and its complement signal

group make up a differential strobe pair. The data is captured

at the crossing point of SA_DQS[7:0] and its SA_DQS#[7:0]

during read and write transactions.

I/O

SA_DQ[63:0]

Data Bus: Channel A data signal interface to the SDRAM data

bus.

I/O

SA_MA[15:0]

Memory Address: These signals are used to provide the

multiplexed row and column address to the SDRAM.

O

SA_CKP[1:0]
SA_CKN[1:0]

SDRAM Differential Clock: Channel A SDRAM Differential

clock signal pair. The crossing of the positive edge of SA_CKP

and the negative edge of its complement SA_CKN are used to

sample the command and control signals on the SDRAM.

O

SA_CS#[1:0]

Chip Select: (1 per rank). These signals are used to select

particular SDRAM components during the active state. There

is one Chip Select for each SDRAM rank.

O

SA_CKE[3:0]

Clock Enable: (1 per rank). These signals are used to:
• Initialize the SDRAMs during power-up
• Power down SDRAM ranks
• Place all SDRAM ranks into and out of self-refresh during

STR

• When 1R DDR3L (SODIMM/MD) CKE[0] is used
• When 2R DDR3L (SODIMM/MD) CKE[1:0] are used

O

SA_ODT

On Die Termination: Active Termination Control.

O

SB_BS[2:0]

Bank Select: These signals define which banks are selected

within each SDRAM rank.

O

SB_WE#

Write Enable Control Signal: This signal is used with

SB_RAS# and SB_CAS# (along with SB_CS#) to define the

SDRAM Commands.

O

SB_RAS#

RAS Control Signal: This signal is used with SB_CAS# and

SB_WE# (along with SB_CS#) to define the SRAM

Commands.

O

SB_CAS#

CAS Control Signal: This signal is used with SB_RAS# and

SB_WE# (along with SB_CS#) to define the SRAM

Commands.

O

SB_DQSP[7:0]
SB_DQSN[7:0]

Data Strobes: SB_DQS[7:0] and its complement signal

group make up a differential strobe pair. The data is captured

at the crossing point of SB_DQS[7:0] and its SB_DQS#[7:0]

during read and write transactions.

I/O

SB_DQ[63:0]

Data Bus: Channel A data signal interface to the SDRAM data

bus.

I/O

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 329001-007

73