Intel i5-4210Y CL8064701558501 Data Sheet

A DisplayPort* consists of a Main Link, Auxiliary channel, and a Hot-Plug Detect signal.

The Main Link is a unidirectional, high-bandwidth, and low latency channel used for

transport of isochronous data streams such as uncompressed video and audio. The

Auxiliary Channel (AUX CH) is a half-duplex bidirectional channel used for link

management and device control. The Hot-Plug Detect (HPD) signal serves as an

interrupt request for the sink device.

The processor is designed in accordance with the VESA DisplayPort* Standard Version

1.2a. The processor supports VESA DisplayPort* PHY Compliance Test Specification

1.2a and VESA DisplayPort* Link Layer Compliance Test Specification 1.2a.

Main Link

(Isochronous Streams)

AUX CH

(Link/Device Managemet)

Hot-Plug Detect

(Interrupt Request)

The High-Definition Multimedia Interface* (HDMI*) is provided for transmitting

uncompressed digital audio and video signals from DVD players, set-top boxes, and

other audiovisual sources to television sets, projectors, and other video displays. It

can carry high quality multi-channel audio data and all standard and high-definition

consumer electronics video formats. The HDMI display interface connecting the

processor and display devices uses transition minimized differential signaling (TMDS)

to carry audiovisual information through the same HDMI cable.

HDMI includes three separate communications channels — TMDS, DDC, and the

optional CEC (consumer electronics control). CEC is not supported on the processor.

As shown in the following figure, the HDMI cable carries four differential pairs that

make up the TMDS data and clock channels. These channels are used to carry video,

audio, and auxiliary data. In addition, HDMI carries a VESA DDC. The DDC is used by

an HDMI Source to determine the capabilities and characteristics of the Sink.

Audio, video, and auxiliary (control/status) data is transmitted across the three TMDS

data channels. The video pixel clock is transmitted on the TMDS clock channel and is

used by the receiver for data recovery on the three data channels. The digital display

data signals driven natively through the PCH are AC coupled and needs level shifting

to convert the AC coupled signals to the HDMI compliant digital signals.

The processor HDMI interface is designed in accordance with the High-Definition

Multimedia Interface with 3D, 4K, Deep Color, and x.v.Color.

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

26

Order No.: 329001-007