Intel Core 2 Quad Q8200 BX80570Q8200 User Manual

16

Datasheet

The processor integrates signal termination on the die. In addition, some of the high 

frequency capacitance required for the FSB is included on the processor package. 

However, additional high frequency capacitance must be added to the motherboard to 

properly decouple the return currents from the front side bus. Bulk decoupling must 

also be provided by the motherboard for proper [A]GTL+ bus operation. 

The Voltage Identification (VID) specification for the processor is defined by the Voltage 

LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage 

to be delivered to the processor VCC lands (see 

 for V

CC

 overshoot 

specifications). Refer to 

 for the DC specifications for these signals. Voltages 

for each processor frequency is provided in

 

To support the Deeper Sleep State the platform must use a VRD 11.1 compliant 

solution. The Deeper Sleep State also requires additional platform support. For further 

information on Voltage Regulator-Down solutions, contact your Intel field 

representative.

Individual processor VID values may be calibrated during manufacturing such that two 

devices at the same core speed may have different default VID settings. This is 

reflected by the VID Range values provided in 

. Refer to the Intel

Q8000, and Q8000S Series Specification Update for further details on specific valid core 

frequency and VID values of the processor. Note that this differs from the VID 

employed by the processor during a power management event (Thermal Monitor 2, 

Enhanced Intel SpeedStep

®

 technology, or Extended HALT State). 

The processor uses eight voltage identification signals, VID[7:0], to support automatic 

selection of power supply voltages. 

 specifies the voltage level corresponding 

to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers 

to a low voltage level. If the processor socket is empty (VID[7:0] = 11111110), or the 

voltage regulation circuit cannot supply the voltage that is requested, it must disable 

itself. The processor provides the ability to operate while transitioning to an adjacent 

VID and its associated processor core voltage (V

CC

). This will represent a DC shift in 

the load line. It should be noted that a low-to-high or high-to-low voltage state change 

may result in as many VID transitions as necessary to reach the target core voltage. 

Transitions above the specified VID are not permitted. 

 includes VID step sizes 

and DC shift ranges. Minimum and maximum voltages must be maintained as shown in 

 and 

as measured across the VCC_SENSE and VSS_SENSE lands.

The VRM or VRD used must be capable of regulating its output to the value defined by 

the new VID. DC specifications for dynamic VID transitions are included in 

. Refer to the Voltage Regulator Design Guide for further details.