Intel Core 2 Quad Q8200 BX80570Q8200 User Manual

Product codes

BX80570Q8200

Datasheet

Electrical Specifications

2.8

Clock Specifications

2.8.1

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous generation processors, the processor core frequency is a

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its

default ratio during manufacturing. The processor supports Half Ratios between 7.5

and 13.5 (see

Table 2-14

for the processor supported ratios).

The processor uses a differential clocking implementation. For more information on the

processor clocking, contact your Intel field representative.

NOTES:
1.

Individual processors operate only at or below the rated frequency.

Listed frequencies are not necessarily committed production frequencies.

Table 2-14. Core Frequency to FSB Multiplier Configuration

Multiplication of System

Core Frequency to FSB

Frequency

Core Frequency

(333 MHz BCLK/

1333 MHz FSB)

Core Frequency

(400 MHz BCLK/

1600 MHz FSB)

Notes

1, 2

1/6

2 GHz

2.6 GHz

1/7

2.33 GHz

2.8 GHz

1/7.5

2.50 GHz

3.0 GHz

1/8

2.66 GHz

3.2 GHz

1/8.5

2.83 GHz

3.4 GHz

1/9

3 GHz

3.6 GHz

1/9.5

3.16 GHz

3.8 GHz

1/10

3.33 GHz

4.0 GHz

1/10.5

3.50 GHz

4.2 GHz

1/11

3.66 GHz

4.4 GHz

1/11.5

3.83 GHz

4.6 GHz

1/12

4 GHz

4.8 GHz

1/12.5

4.16 GHz

5.0 GHz

1/13

4.33 GHz

5.2 GHz

1/13.5

4.50 GHz

5.4 GHz

1/14

4.66 GHz

5.6 GHz

1/15

5 GHz

5.8 GHz