Intel i7-4600U CL8064701477000 Data Sheet

DTS indicates that it has reached the TCC activation (a reading of 0h, except when the

TCC activation offset is changed), the TCC will activate and indicate an Adaptive

Thermal Monitor event. A TCC activation will lower both IA core and graphics core

frequency, voltage, or both. Changes to the temperature can be detected using two

programmable thresholds located in the processor thermal MSRs. These thresholds

have the capability of generating interrupts using the core's local APIC. Refer to the

 64 and IA-32 Architectures Software Developer’s Manual for specific register

and programming details.

The error associated with DTS measurements will not exceed ±5 °C within the entire

operating range.

Digital Thermal Sensor based fan speed control (T

FAN

) is a recommended feature to

achieve optimal thermal performance. At the T

FAN

 temperature, Intel recommends full

cooling capability well before the DTS reading reaches Tj

MAX

.

PROCHOT# (processor hot) is asserted when the processor temperature has reached

its maximum operating temperature (Tj

MAX

). Only a single PROCHOT# pin exists at a

package level. When any core arrives at the TCC activation point, the PROCHOT#

signal will be asserted. PROCHOT# assertion policies are independent of Adaptive

Thermal Monitor enabling.

By default, the PROCHOT# signal is set to bi-directional. However, it is recommended

to configure the signal as an input only. When configured as an input or bi-directional

signal, PROCHOT# can be used for thermally protecting other platform components in

case the components overheat as well. When PROCHOT# is driven by an external

device:
•

The package will immediately transition to the lowest P-State (Pn) supported by

the processor and graphics cores. This is contrary to the internally-generated

Adaptive Thermal Monitor response.

•

Clock modulation is not activated.

The processor package will remain at the lowest supported P-state until the system

de-asserts PROCHOT#. The processor can be configured to generate an interrupt upon

assertion and de-assertion of the PROCHOT# signal.

When PROCHOT# is configured as a bi-directional signal and PROCHOT# is asserted

by the processor, it is impossible for the processor to detect a system assertion of

PROCHOT#. The system assertion will have to wait until the processor de-asserts

PROCHOT# before PROCHOT# action can occur due to the system assertion. While the

processor is hot and asserting PROCHOT#, the power is reduced; however, the

reduction rate is slower than the system PROCHOT# response of < 100 us. The

processor thermal control is staged in smaller increments over many milliseconds. This

may cause several milliseconds of delay to a system assertion of PROCHOT# while the

output function is asserted.

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

68

Order No.: 329001-007