Intel C2550 FH8065401488912 Data Sheet

Product codes
FH8065401488912
Page of 746
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
135
Volume 2—SoC Reset and Power Supply Sequences—C2000 Product Family
Reset Sequences and Power-Down Sequences
Figure 7-4. S0 State to S5 State Sequence
RTC power well and SUS power well 
voltages are valid during this entire period
t
56
t
582
Voltage supply power-down 
sequence may start anytime 
after here. See text.
These SoC inputs are 
in the de-asserted 
state during entire 
period: RTEST_B
SRTCRST_B
RSMRST_B
SoC output:
SUSPWRDNACK
SoC output: 
PMU_SLP_S3_B
SoC output: 
PMU_SLP_DDRVTT_B
SoC output: 
PMU_PLTRST_B
All Core well voltages valid 
at SoC input pins
SoC output: 
SUS_STAT_B
SoC output: 
CPU_RESET_B
SoC input: 
COREPWROK
SoC inputs: 
DDR3_0_VCCA_PWROK
DDR3_1_VCCA_PWROK
SoC output: 
PMU_SLP_S45_B
For Cold Reset Sequence
For Stay in S5 Sequence
SoC inputs: 
DDR3_0_DRAM_PWROK
DDR3_1_DRAM_PWROK
t
61
t
602
VDDQ voltages valid at 
SoC input pins