Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

142

Order Number: 330061-002US

While deasserted by the platform board, the active-low Resume Well Reset 

(RSMRST_B) signal indicates to the SoC that the platform board is supplying valid SUS 

well power to the SoC. If the platform board asserts RSMRST_B during the S5 state, 

the SoC enters the G3 (Mechanical Off) state and the platform board may power-down 

the SoC SUS well (standby) voltages. The power-down sequence of the SoC SUS well 

(standby) voltages is shown in 

In the S5 state, the DDR3 and the SoC Core well power is off. The platform board 

powers down the SoC SUS well (standby) voltages in the following manner:

All voltage-supply sequencing requirements are given as measured at the SoC pins/

balls.

a. V3P3A
b. V1P0A
c. V1P8A

— Optionally, the following SUS well power-down sequence may be used:

a. V3P3A
b. V1P8A
c. V1P0A

It is permissible for V1P8A and V1P0A to be powered-up at the same time, but it is best 

to stagger their ramp-up as indicated here.

VRTC3P0 Voltage Valid

SoC input:

SoC input:

All Standby Voltages Valid

and GbE Reference Clock 

stable at SoC input pins

SoC input:

SoC input:

SoC output:

SoC output: