Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

150

Order Number: 330061-002US

Thermal Control Circuit (TCC) mechanisms are implemented to reduce temperature by 

reducing power consumption in response to a Core HOT condition. The core implements 

Intel

®

 Thermal Monitor 1 (TM1) clock modulation similar to legacy devices and Intel

®

 

Thermal Monitor 2 (TM2) core frequency/voltage reduction. All thermal control circuit 

mechanisms are controlled via P-Unit routines. 

Intel

®

 Thermal Monitor 1 (TM1) effectively stops the core clock periodically to reduce 

processor power consumption. The duration for which the clock is modulated is 

programmable within each core register. The on/off duty-cycle is adjusted in 

increments of 12.5% and must be configured by the BIOS. 

The stop-clock duration is frequency dependent and higher frequencies stop the clock 

for shorter durations for a given duty-cycle configuration.

TM1 is enabled via each core register and activated as a secondary control mechanism 

if TM2 (described below) is unsuccessful at reducing processor temperatures for a 

period of time.

The core implements an adaptive Intel

®

 Thermal Monitor 2 (TM2) mechanism which 

transitions to a lower operating frequency and voltage Low Frequency Mode (LFM). The 

core implements this mechanism only if higher performance frequency and voltage 

points are not successful in reducing temperatures (i.e., chooses the highest 

performance operating point which reduces processor temperatures). 

Intel

®

 Thermal Monitor 2 is automatically selected as the primary thermal control 

mechanism and selection of LFM versus adaptive mode is achieved via the thermal 

configuration registers.

Thermal trip events are captured in status registers. Associated with each event is a set 

of programmable actions. For a complete list of refer to the Avoton/Rangeley SoC BIOS 

.