Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

165

This section describes the concept of processor and device performance states. 

Processor and device performance states (Px states) are power consumption and 

capability states within the active/executing states, C0 for processors and D0 for 

devices. Performance states allow the Operating System Power Management (OSPM) to 

make trade-offs between performance and energy conservation. Processor and device 

performance states have the greatest impact when the states invoke different device 

and processor efficiency levels as opposed to a linear scaling of performance and 

energy consumption. Since performance state transitions occur in the active/executing 

device states, ensure that performance state transitions do not adversely impact the 

system.

Disabling the software from requesting P-States is possible by setting bit 16 in 

IA32_MISC_ENABLE. This does not prevent the SoC changing frequency in voltage for 

thermals, RAPL, and PkgC1E.

The SoC supports P-States for every dual-core pair within a module. Based on power 

performance analysis, the SoC only support Package Level P-States. The Power 

Management Unit will select the highest P-state from all requests across all modules 

and apply that state to all cores. The internal power management sets a lock bit to 

ensure that the cores are always at the same P-State.

SoC CPU supports P-States for OS-controlled management of processor performance. 

The CPU range of operation is broken down into P-States and T-States.

Operating systems which support ACPI may utilize the BIOS FADT table to map ACPI P-

States. 

 describes ACPI P-State mappings.

The OS requests a P-State based on application performance needs. A desired P-State 

is requested via IA32_PERF_CTL (CLOCK_CR_GEYSIII_CONTROL). The SoC supports 

the Enhanced Intel SpeedStep

®

 Technology.

P0

Performance is preferred over power 

efficiency

Greater-than or equal-to the Maximum Non-

Turbo Limit Ratio.
This is set based on thermal/electrical limits, 

platform constraints, and other parameters.

P1

Maximum performance/efficiency is 

desired

Maximum Non-Turbo Limit Ratio (Guaranteed 

Ratio)

P2 through PN

Intermediate performance/efficiency is 

desired

Less-than the Maximum Non-Turbo Limit Ratio,
Greater-than the Maximum Efficiency Ratio

PN

Maximum performance efficiency is 

desired (best for average power)

Maximum Efficiency Ratio correlates to minimum 

operational voltage (LFM_RATIO)