Intel C2550 FH8065401488912 Data Sheet
Product codes
FH8065401488912
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
169
Volume 2—Power Management—C2000 Product Family
Voltage Identification (VID) Table
9.11.2
Running Average Power Limiting (RAPL)
The SoC contains proprietary power monitors and Running Average Power Limit (RAPL)
algorithms that calculate an energy budget and convert the budget into voltage/
frequency working points.
The SoC supports RAPL control through these SoC interfaces:
• Memory-Mapped I/O (MMIO) interface for drivers to program RAPL limits and
monitor RAPL performance.
• Platform Environment Control Interface (PECI) via SMBus for the platform firmware
to program RAPL limits and monitor RAPL performance.
• I/O Port CF8/CFC for registers not mapped to MSR or MMIO space.
9.11.3
Always-On Timers (AONT)
Always-On Timers run while the CPU/SoC is in the S0 state, including the S0 idle state,
and are used to periodically wake-up the cores from sleeping. They do not run when
the CPU transitions out of S0.
9.11.4
I/O Device Controller Enable/Disable
9.12
Voltage Identification (VID) Table
§ §
Table 9-12. I/O Power Management Summary
Integrated
I/O Device
I/O Feature Not Used
by Customer
Nothing Connected to
Interface at Boot Time
PC6 Idle (S0idle)
PCIe* Root Ports
The BIOS disables the
circuitry and power on a
per-lane basis.
The BIOS disables the
circuitry and power on a
per-lane basis.
Depending on the product SKU,
internal clocks off and power
gated from controller.
SATA2
The BIOS disables the
circuitry and power-on a
per-port basis.
Disabled at power-on
unless explicitly enabled by
the software.
Depending on product SKU,
disabled and power gated from
controller or internal clocks off.
SATA3
The BIOS disables the
circuitry and power-on a
per-port basis.
Disabled at power-on
unless explicitly enabled by
the software.
Depending on product SKU,
disabled or internal clocks off.
GbE
The BIOS disables the
circuitry and power-on a
per-port basis.
Ports not WOL-enabled are
in P2.
Ports with WOL are in P0.
If all ports are WOL-
disabled, internal clocks off.
Ports not WOL-enabled are in
P2.
Ports with WOL are in P0.
If all ports are WOL-disabled,
internal clocks off.
USB
The BIOS disables the
circuitry and power.
Idle State with internal
clocks off.
Idle state with internal clocks
off.
Table 9-13. VID Range and Power State Support
VID Range
Required Power State Support
VID greater than 0.5V
PS0, PS1, PS2, PS3
VID = 0.5V
PS0, PS1, PS2, PS3
VID less than 0.5
PS2, PS3