Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

197

PCI Device and Function presence or non-presence must be established before PCI 

enumeration and before the integrated GbE controller is released from PCI Reset. Soft 

Straps for the GbE controller are provided for this purpose.

For a given product SKU, the SoC Soft Strap settings are the first setup parameters 

applied to the SoC devices. The Soft Strap settings are applied to the SoC devices while 

the platform and integrated PCI devices are still reset. In this reset state, the 

integrated GbE controller maps PCI function 0 to LAN Port 0, function 1 to LAN Port 1, 

etc.

There are four SoC Soft Straps that affect the four LAN Ports. By default, all LAN Ports 

(and PCI functions) of a particular product SKU are enabled. LAN Ports (and possibly 

their corresponding PCI function) 1, 2, and 3 can be disabled by setting its Soft Strap to 

a 1. The GBE_ALL_DISABLE Soft Strap, if set, overrides the settings of the three Soft 

Straps for LAN Ports 1, 2, and 3. When set, the GBE_ALL_DISABLE Soft Strap also 

disables LAN Port 0. See 

.

When set to a “1,” the GBE_ALL_DISABLE Soft Strap, the GbE controller is not 

enumerated, and so, does not exist. In this case, and if the system-management 

capabilities of the integrated GbE controller are not wanted, the GbE EEPROM is not 

needed in the platform design.

Support in S5 for Wake-on-LAN and/or Manageability requires setting the ‘GbE 

powered in S5’ bit in the Flash Descriptor soft straps. With this soft strap set the GbE 

MAC will retain connection through type 1 and 3 system resets.

If the GbE Controller is configured to provide the 50-MHz NC-SI “REF_CLK” signal to 

the rest of the platform board via the NCSI_CLK_IN signal (pin P50, an output as well 

as an input), then the GBE_ALL_Disable Soft Strap must be a “0” (at least Function 0 of 

the device is enabled).