Intel C2550 FH8065401488912 Data Sheet
Product codes
FH8065401488912
Volume 2—PCI Express Root Ports (RP)—C2000 Product Family
Configuration of PCI Express Ports and Link Widths
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
236
Order Number: 330061-002US
12.8.2.1
SoC PCI Express Lanes Mapping
summarizes the PCIe* lanes and PCIe controller mapping for various SoC
SKUs
Table 12-9. PCIe Lanes and PCIe Controller Mapping for Various SKUs
PCIe
CTRL
/Lane
Config
CTRL
/Lane
Config
Softstrap
1
0
PCIe RP
Disable
Disable
RP4 RP3 RP2 RP1
Softstrap
8
PCIe RP
Disable
Disable
RP4 RP3 RP2
RP1
Softstrap 5
PCIe Lane
Power
Enable
[15:12][11:8][7:4][3:0
]
Softstrap 8
SlotWidth
12 bits total, 3 bits per RP
Bifurcation
Controller
Register
BIFCTL0
L
a
a
n
e
e
15
L
a
a
n
e
e
14
L
a
a
n
e
e
13
L
a
a
n
e
e
12
L
a
a
n
e
e
11
L
a
a
n
e
e
10
L
a
a
n
e
e
9
L
a
a
n
e
e
8
L
a
a
n
e
e
7
L
a
a
n
e
e
6
L
a
a
n
e
e
5
L
a
a
n
e
e
4
L
a
a
n
e
e
3
L
a
a
n
e
e
2
L
a
a
n
e
e
1
L
a
a
n
e
e
0
x16 Lanes with 4 Controllers SKUs
4x4
default = 0000 default = 0000
default = FFFF
default = 0_0_0_0
000
RP4
RP3
RP2
RP1
1x8, 2x4
default = 0000 default = 0000
default = FFFF
default = 0_0_0_0
001
RP4
RP3
RP1
2x4, 1x8
default = 0000 default = 0000
default = FFFF
default = 0_0_0_0
010
RP3
RP2
RP1
2x8
default = 0000 default = 0000
default = FFFF
default = 0_0_0_0
011
RP3
RP1
4x16
default = 0000 default = 0000
default = FFFF
default = 0_0_0_0
100
RP1
x8 Lanes with 4 Controllers
3
SKUs
4x4
default = 0000 default = 0000
default = FFFF
default = 0_0_0_0
000
RP4
RP3
RP2
RP1
1x8
4'b1100
4'b1100
16'h0_0_F_F
default = 0_0_0_0
001
RP4
RP3
RP1
2x4
4'b1100
4'b1100
16'h0_0_F_F
default = 0_0_0_0
010
RP3
RP2
RP1
1x4
4'b1101
4'b1101
16'h0_0_F_0
default = 0_0_0_0
000
RP4
RP3
RP2
RP1
4x2
default = 0000 default = 0000
default = FFFF
12'b010_010_010_010
000
RP4
RP3
RP2
RP1
4x1
default = 0000 default = 0000
default = FFFF
12'b001_001_001_001
000
RP4
RP3
RP2
RP1
x8 Lanes with 2 Controllers SKUs
2x4
default = 0000 default = 0000
default = FFFF
default = 0_0_0_0
000
RP4
RP3
RP2
RP1
1x8
default = 0000 default = 0000
default = FFFF
default = 0_0_0_0
001
RP4
RP3
RP1
2x4
default = 0000 default = 0000
default = FFFF
default = 0_0_0_0
010
RP3
RP2
RP1
1x8
default = 0000 default = 0000
default = FFFF
default = 0_0_0_0
011
RP3
RP1
x4 Lanes with 4 Controllers
4
SKUs
1x4
4'b1101
4'b1101
16'h0_0_F_0
default = 0_0_0_0
000
RP4
RP3
RP2
RP1
2x2
4'b1001
4'b1001
16'h0_F_F_0
12'b000_001_001_000
000
RP4
RP3
RP2
RP1
4x1
default = 0000 default = 0000
default = FFFF
12'b000_001_001_001
000
RP4
RP3
RP2
RP1
x4 Lanes with 1 Controller SKUs
1x4
default = 0000 default = 0000
default = FFFF
default = 0_0_0_0
000
RP4
RP3
RP2
RP1
1x4
default = 0000 default = 0000
default = FFFF
default = 0_0_0_0
010
RP3
RP2
RP1
L e g e n d
D e s c r i p t i o n
P C I e L a n e i s p o w e r e d a n d e n a b l e d
P C I e L a n e i s n o t a v a i l a b l e i n t h i s S K U
P C I e L a n e i s p o w e r e d b u t d i s a b l e d v i a s o f t s t r a p
S t r a p 8 : S l o t W i d t h P a r a m e t e r
S t r a p 8 : S l o t W i d t h P a r a m e t e r
P C I e L a n e i s u n ‐ p o w e r e d a n d d i s a b l e d v i a s o f t s t r a p s
S t r a p 0 a n d S t r a p 8 : P C I e R P x D i s a b l e P a r a m e t e r
S t r a p 5 : P C I e L a n e y P o w e r E n a b l e P a r a m e t e r
x = p o r t n u m b e r ( 1 ‐ 4 ) , y = l a n e n u m b e r ( 0 ‐ 1 5 )
S t r a p 0 a n d S t r a p 8 : P C I e R P x D i s a b l e P a r a m e t e r
S t r a p 5 : P C I e L a n e y P o w e r E n a b l e P a r a m e t e r
x = p o r t n u m b e r ( 1 ‐ 4 ) , y = l a n e n u m b e r ( 0 ‐ 1 5 )
*