Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

252

Order Number: 330061-002US

After the interface and device have been put into a low-power state, the SATA host 

controller is put into a low-power state. This is performed using the PCI power 

management registers in configuration space. 

Two important aspects when using PCI power management:

1. When the power state is D3, only accesses to configuration space are allowed. Any 

attempt to access the memory or I/O spaces results in master abort.

2. When the power state is D3, no interrupts are generated, even if they are enabled. 

If an interrupt status bit is pending when the controller transitions to D0, an 

interrupt is generated.

When the controller is put into D3, the assumption is that the software has properly 

shut down the device and disabled the ports. Sustaining any values on the port wires is 

not needed. The interface is treated as if a device is not present on the cable, and 

power is minimized.

When returning from a D3 state, an internal reset is not performed.

When in non-AHCI mode (legacy mode) of operation, the SATA controller does not 

generate PME#. This includes attach events (since the port must be disabled), or 

interlock switch events (using the SATA_GP0 pin).