Intel C2550 FH8065401488912 Data Sheet
Product codes
FH8065401488912
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
259
Volume 2—SATA Controllers (SATA2, SATA3)—C2000 Product Family
Bus Master IDE I/O Registers
13.6
Bus Master IDE I/O Registers
This controller implements IDE Bus Master registers and ATA task file shadow registers.
All these I/O registers are in the core well. All I/O registers are reset by FLR.
registers are not mapped and not accessible; only 16 bytes of I/O space are allocated.
When CC.SCC is not 01h, all registers are mapped and accessible; 32 bytes of I/O
space are allocated.
13.7
Serial ATA Index/Data Pair Superset Registers
All of these I/O registers are in the core well. They are exposed only when CC.SCC is
01h (i.e., IDE programming interface).
These are Index/Data Pair registers that are used to access the SerialATA superset
registers (SerialATA Status, SerialATA Control and SerialATA Error). The I/O space for
these registers is allocated through SIDPBA. Locations with offset from 08h to 0Fh are
reserved for future expansion. Software write operations to the reserved locations has
no effect while the software read operations to the reserved locations return 0.
Table 13-7. Summary of I/O Registers—LBAR
Offset Start
Offset End
Register ID—Description
0h
0h
“PCMD (PCMD)—Offset 0h”
2h
2h
“PSTS (PSTS)—Offset 2h”
4h
7h
“PDTP (PDTP)—Offset 4h”
8h
8h
“SCMD (SCMD)—Offset 8h”
Ah
Ah
“SSTS (SSTS)—Offset Ah”
Ch
Fh
“SDTP (SDTP)—Offset Ch”
10h
13h
“INDEX (INDEX)—Offset 10h”
14h
17h
“DATA (DATA)—Offset 14h”
Table 13-8. Summary of I/O Registers—ABAR
Offset Start
Offset End
Register ID—Description
0h
3h
“SINDX (SINDX)—Offset 0h”
4h
7h
“SDATA (SDATA)—Offset 4h”