Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

297

Certain SMBus protocols are disallowed in target mode since they violate the hardware-

firmware descriptor mechanism. First, the descriptor is passed to the firmware only 

after the transaction stop; this architecture does not permit the firmware to return a 

payload within the same transaction. Second, waiting for a descriptor from the 

firmware requires the hardware to perform excessive SMBus clock-stretching.

 captures the responses of the hardware/firmware under the various 

combinations of ARP protocol, address and UDID fields, and ARP status flags. The 

states mentioned refer to 

1. Hardware checking of LSB during start address cycle is controlled by SUSCHKB.IRWST. (Applies to SMBus

target addresses, C2h, and 10h.) See also 

 for

more implications to the firmware and the hardware regarding IRWST.

ARP protocols applicable to all SMT UDIDs

C2h

01h

n/a

Prepare to ARP

C2h

02h

n/a

Reset Device (general)

C2h

03h

n/a

Get UDID (general)

2. Hardware checking of LSB during repeated-start address cycle is controlled by SUSCHKB.IRWRST. (Applies to

SMBus target addresses and C2h.)

n/a

n/a

Get UDID (general) —after repeated start

ARP protocols specific to only matched UDID (128 bits)

C2h

04h

Matches an 

SMT UDID

Assign Address

ARP protocols specific to only matched slave address (7 bits)

C2h

{target address, 1}

n/a

Get UDID (directed)

n/a

n/a

Get UDID (directed) —after repeated start

C2h

{target address, 0}

n/a

Reset Device (directed)

10h

C2h

n/a

Notify ARP master

10h

!= C2h

3

3. For a transaction directed to 10h if the command byte is not C2h then the transaction is SMBus Host Notify

and the command code format is {initiator slave address, 0}. 

n/a

SMBus Host Notify

Ordinary SMBus (and I

2

C) protocol specific to only matched slave address (7 bits)

{slave address, x}

n/a

n/a

Ordinary SMBus transaction.
LSB = x to be protocol agnostic

• Quick Command
• Send  Byte
• Write Byte/Word
• Block Write
• Block Read

{slave address, 1}

n/a

n/a

Ordinary SMBus transaction.
LSB = 1 —after repeated start

• Block Read