Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

307

0

31

SOE

: This bit is set to 1 to direct the hardware that if a descriptor-

based master cycle results in an unsuccessful transaction on SMBus, the 

hardware must clear the start/stop bit (MCTRL.SS) and stop the engine.
If this bit is clear, if the hardware encounters an error while sending a 

transaction on SMBus, it sets the master error status bit (MSTS.MEIS) and 

continue to process the next descriptor in the queue.

0

30

INT

: This bit is set to 1 to direct the hardware that it must generate 

an MSI to the firmware when it has completed the requested transaction 

successfully. This interrupt is generated only after the status Dword of the 

descriptor is written back to memory. 
Interrupts due to unsuccessful transactions on SMBus are not affected by 

this bit.
If this bit is clear and the transaction is successful on SMBus, no interrupt is 

generated; however, the firmware polls the MSTS.MIS bit.

When using legacy interrupts this bit has no effect; a legacy 

interrupt is always generated even if not requested by master 

descriptor (firmware).

0

29

I

2

C

I

2

C Enable: This bit is set to 1 to indicate the hardware must perform the 

transaction using I

2

C protocol.

0

28

PEC

: This bit is set to 1 to indicate the hardware must 

append CRC (or PEC) as the master of the requested transaction if it is a 

write or check received CRC (PEC) of the requested transaction if it is a read. 

PEC is calculated over the entire message (including address and read/write 

bits) and supplied by the device which puts out the last-data byte of the 

message.

0

27

FAIR

: This bit is set to 1 to indicate if the hardware is able to successfully win 

arbitration on the bus and master the transaction, it must set its internal 

fairness flag.
This allows a mechanism for fairness on SMBus per MCTP Specification.

0

26

BLK

: Set to 1 by the firmware to indicate the hardware must perform a 

Block Transaction on the bus. The hardware determines one of three block 

transactions based on the following fields
{BLK, C/WRL and R/W}.
100: Perform SMBus Block Write
111: Perform SMBus Block Read
101: Perform SMBus Block Process Call
Others: Reserved

0

25

Reserved

Reserved

0

24

C/WRL

: Set to 1 by the firmware when it has overloaded 

the Write Length field with the command code of the SMBus transaction.

0

23:16

RDLNTH

: Indicates the number of bytes the hardware receives from 

the target, and write to the receive data buffer 1-based counting, i.e., the 

value 0h means 0 bytes of receive data and the value Ah means 10 bytes of 

receive data. The maximum read length currently supported by the hardware 

is 240 bytes due to its internal buffer size.

0

15:8

WRLNTH

: Indicates the number of bytes the hardware transmits as 

master (except the first address byte, byte count, and any subsequent 

address bytes for reads) 1-based counting, i.e., the value 0h means 0 bytes 

of transmit data and the value Ah means 10 bytes of transmit data. The 

maximum write length supported by the hardware is 240 bytes including 

address due to the size of its internal buffer. The byte count for the SMBus 

transactions is calculated by the hardware based on the write length field. 

Example: if WRLNTH = 8, the hardware calculates byte count = 7 and send 

on the SMBus. The WRLNTH field itself contains command code and 7 bytes 

of data. When the C/WRL flag is set, this field contains the command code of 

the SMBus transaction.