Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

321

31:24

PBC

The hardware updates this field to indicate how many bytes of 

payload data follows after the header in the target buffer. For writes coming in, this data 

include the sum total of all bytes ACKed from start to stop. The hardware does then DMA 

all those bytes to memory. 

• For error scenarios where the master drives more data than expected or command 

code does not match, the hardware does DMA all bytes ACKed on SMBus from Start 

until the first byte NACKed by the hardware (this byte is not sent to memory), and 

the total number of bytes DMAed to memory is reflected in this field.

A value of all zeros in this field means no payload is following the header. 

23:22

Reserved

Reserved

21:16

RBC

: For external master-generated reads, this data include the sum total 

of bytes provided by the hardware which were successfully transferred over SMBus. For 

example: for an externally generated block read, the hardware provides byte count, X 

number of bytes, and PEC (if PEC-enabled transaction). In this case, the RBC field is 

1+X+1 (for PEC).

For SMBus Block Reads, the last byte transferred is NACked by the external 

master per definition. This is data byte or PEC byte supplied by the hardware. 

The data bytes are not written to memory, only the byte count indicates how many 

bytes provided by the hardware were successfully transferred over SMBus.
This field is all zeros if the transaction was an externally-generated write.
The header is written to memory (if enabled to do so) containing the status of the 

transaction.
For error scenarios in reads, the status register in the header provides details of the 

error and this field contains incorrect values due to the pipelined nature of the hardware.

15:12

Reserved

 Reserved

11:8

MTYPE

: These bits indicate which expected transaction happened on the bus 

since they are expected in the usage model and some have pre-programmed data 

provided by the firmware.
0000: SMBus/I

2

C transaction

0111: Block Read to General Purpose Read Data Buffer
1000: SMBus ARP Prepare to ARP
1001: SMBus ARP Reset Device (general)
1010: SMBus ARP Get UDID (general)
1011: SMBus ARP Assign Address
1100: SMBus ARP Get UDID (directed)
1101: SMBus ARP Reset Device (directed)
1111: SMBus ARP Notify ARP Master or SMBus Host Notify
Others: Reserved

Firmware: The cycle does not progress far enough for the hardware to encode 

the correct encodings. In this case, the hardware inserts some reserved value.