Intel C2550 FH8065401488912 Data Sheet
Product codes
FH8065401488912
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
325
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Controller Characteristics and Operation
0001
Cycles to
Cycles to
ADDR0/
UDID0
or
0010
Cycles to
or
0010
Cycles to
ADDR1/
UDID1
or
0000
Cycles to
or
0000
Cycles to
Default
Address
No
errors
PEC received
from the
external
master did
not match the
hardware-
calculated
PEC.
Note:
Note:
This is
a speculative
error only
since the
firmware
confirms it
was a PEC-
enabled
SMBus
transaction
(see
).
• A collision is
detected by the
hardware. This
happens when
the hardware
intended to drive
NACK and saw
an ACK on the
bus.
• The external
master signals
stop/restart,
etc. in the
middle of a byte.
• The external
master signals
stop on a byte
boundary before
the byte count
expired.
• The external
master drives
more bytes than
indicated by the
byte count.
• The external
master
generates start
instead of stop
on a byte
boundary as a
response to the
hardware NACK
in the previous
data phase.
• The hardware
NACKs when
the external
master drives
more data than
the limit
programmed in
TRxCTRL.MRxB
• The hardware
detects the
protocol/
address
violation (see
and
).
N/A (the
hardware
does not
provide any
bytes)
The hardware
detects the
SMBus clock
low time-out
anywhere in
the middle of
the
transaction
that it is
actively
servicing.
The
hardware
detects the
SMBus data
low time-out
anywhere in
the middle of
the
transaction
that it is
actively
servicing.
0100
Host
Host
Notify or
Notify
ARP
Master
No
errors
N/A (no PEC)
• A collision
detected by
hardware. This
happens when
the hardware
intended to drive
NACK and saw
an ACK on the
bus.
• The external
master signals
stop/restart,
etc. in the
middle of a byte.
• The external
master signals
stop on a byte
boundary before
it sends 3-data
bytes.
• The external
master drives
more than
3-data bytes
after the
address phase.
N/A (the hardware
does not check any
bytes)
N/A (the
hardware
does not
provide any
bytes)
The hardware
detects the
SMBus clock
low time-out
anywhere in
the middle of
the
transaction
that it is
actively
servicing.
The
hardware
detects the
SMBus data
low time-out
anywhere in
the middle of
the
transaction
that it is
actively
servicing.
Table 15-19. Target Header Encodings (TSTS) Per Transaction Type (TTYPE) (Sheet 2 of 2)
TTYPE
Cycle
Type
TSTS
0000
Success
TSTS 0001
PEC Error
TSTS
0010
Protocol Error
TSTS
0011
Hardware NACK
TSTS
0100
External
NACK
TSTS
0101
Clock Low
Time Out
TSTS
0110
Data Low
Time Out