Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

343

Since the target ring buffer is a single buffer in the memory, the interrupts sent on 

behalf of the target are simplified to be sent every time the hardware writes data and/

or header to the memory (depending on if Target interrupts are enabled and if global 

MSIen is set).

The conditions which result in a status header being written are further governed by 

these policies:

• TCTRL.SCHWBP: upon successful completion of target cycles.
• TCTRL.UCHWBP: upon unsuccessful completion of target cycles.
• TCTRL.URxTWP: upon unsuccessful completion of writes to target.

This simplified model is used since the hardware supports multiple logical devices and 

transactions of each type are pushed to memory by the hardware in a sequential 

manner. The firmware then has to parse each header to determine what each 

transaction is before the firmware takes appropriate action.

A single Target Interrupt Enable bit is maintained in MMIO space (TCTRL.TIE) which 

gates the sending of this interrupt. An associated status bit (TSTS.TIS) is also 

maintained in the hardware.

Similar to master interrupts, target interrupts are also serialized and ordered. The 

decision to send MSI is made after the hardware has written back the header for the 

received transaction to the memory ring buffer.

1. Receive target cycle from SMBus.
2. Perform data and header WB to memory.
3. Write 1 to the appropriate Cause Status bit (TSTS.TIS).

If TCTRL.TIE is enabled (locally and globally), MSI is sent and the cause status is auto 

cleared else MSI is not sent and cause remains set.

Firmware implementation:

1. If the cause is set for a previous target transaction written to memory and the 

firmware enables the global (and local) interrupt enable, the hardware does not 

send an interrupt for a previously set cause.

2. It is the responsibility of the firmware to ensure that if the cause is set, the 

previous transactions are accounted for before enabling MSI (globally and locally).