Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

429

The SoC provides multiple System Management Bus (SMBus) 2.0 controllers. The 

SMBus controller described in this chapter is located in the Platform Control Unit (PCU) 

of the SoC. In SoC diagrams, it is labeled SMBus0.

The host controller provides a mechanism for the processor to initiate communications 

with SMBus peripherals (slaves). The SoC is also capable of operating in a mode that 

communicates with I

2

C-compatible devices.

The SoC performs SMBus messages with Packet Error Checking (PEC) enabled or 

disabled. The actual PEC calculation and checking are performed in either the hardware 

or the software.

The SMBus Address Resolution Protocol (ARP) is supported by using the existing host 

controller commands through the software, except for the Host Notify command (which 

is actually a received message).

SMBus

2.0

August 3, 2000

 Version 2.0

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Platform Controller Unit

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