Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

461

When the receive FIFO and receiver interrupts are enabled (FIFO Control Register, 

bit 0 = 1b and Interrupt Enable Register (IIR), bit 0 = 1b), receiver interrupts occur as 

follows:

• The receive data available interrupt is invoked when the FIFO has reached its 

programmed trigger level. The interrupt is cleared when the FIFO drops below the 

programmed trigger level.

• The IIR receive data available indication also occurs when the FIFO trigger level is 

reached, and like the interrupt, the bits are cleared when the FIFO drops below the 

trigger level.

• The receiver line status interrupt (IIR = C6h), as before, has the highest priority. 

The receiver data available interrupt (IIR = C4h) is lower. The line status interrupt 

occurs only when the character at the top of the FIFO has errors.

When the receiver FIFO and receiver time out interrupt are enabled, a character time 

out interrupt occurs when all of the following conditions exist:

• At least one character is in the FIFO.
• The last received character was longer than four continuous character times ago (if 

two stop bits are programmed, the second one is included in this time delay).

• The most recent processor read of the FIFO was longer than four continuous 

character times ago.

• The receiver FIFO trigger level is greater than one.

The maximum time between a received character and a time-out interrupt is 160 ms at 

300 baud with a 12-bit receive character (i.e., one start, eight data, one parity, and two 

stop bits).

When a time out interrupt occurs, it is cleared and the timer is reset when the 

processor reads one character from the receiver FIFO. If a time out interrupt has not 

occurred, the time out timer is reset after a new character is received or after the 

processor reads the receiver FIFO. 

When the transmitter FIFO and transmitter interrupt are enabled (FIFO Control 

Register, bit 0 = 1b and Interrupt Enable Register, bit 0 = 1b), transmit interrupts occur 

as follows: 

• The transmit data request interrupt occurs when the transmit FIFO is half empty or 

more than half empty. The interrupt is cleared as soon as the Transmit Holding 

Register is written (1 to 16 characters are written to the transmit FIFO while 

servicing the interrupt) or the Interrupt Identification Register is read.