Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 1 of 3

Order Number: 330061-002US

47

The SoC core is designed using 22nm process technology for use in ultra-low-power 

applications. Each SoC module, called a CMP, incorporates dual CPU cores, a bus 

interface unit (BIU) and a 1 MB L2 cache.

The features of each SoC Module are:

• 2-wide out-of-order (OOO) scheduler
• Chip-Level Multi Processing (CMP). No support for hyper-threading technology. 
• One thread per core
• Improved instruction fetch and decode functions
• Better branch predictors
• Improvements to TLB and caching hierarchy
• Hybrid OOO scheduling and OOO cache miss processing
• Per core-power gating support
• Intel

®

 Streaming SIMD Extensions 4.1 and 4.2 (SSE4.1 and SSE4.2).

• Intel

®

 64 architecture

• Support for IA-32 instruction set
• Support for Intel

®

 Virtualization Technology (Intel

®

 VT) for IA-32, Intel

®

 64 and 

Intel

®

 Architecture (Intel

®

 VT-x)

• Support for Intel

®

 Advanced Encryption Standard New Instructions (AES-NI)

• Support for a Digital Random Number Generator (DRNG)
• Intel

®

 Turbo Boost Technology

• Supported C-states: C0, C1, C6C. The C4 state is not supported.