Intel C2550 FH8065401488912 Data Sheet
Product codes
FH8065401488912
Volume 2—Serial Peripheral Interface (SPI)—C2000 Product Family
Signal Descriptions
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
472
Order Number: 330061-002US
22.1
Signal Descriptions
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction is either input, output, or I/O (bi-directional)
• Type: The buffer type
• Description: A brief explanation of the signal function
• Direction: The buffer direction is either input, output, or I/O (bi-directional)
• Type: The buffer type
• Description: A brief explanation of the signal function
22.2
SPI Features
The following are the SPI features:
• Support for up to two SPI Flash devices.
— Storage capacity may be different.
— Both devices must be from the same vendor and family.
— Both devices must be from the same vendor and family.
• Supports five configurable protecting ranges.
• SoC soft-strap information is supported only in the SPI Flash mode.
• Maximum addressability is 16 MB for each SPI device.
• SoC soft-strap information is supported only in the SPI Flash mode.
• Maximum addressability is 16 MB for each SPI device.
All I/O signals are 3.3V and the I/O circuitry is in the Suspend (SUS) power well. The
rest of the SPI controller resides in the core power well. During the S5 state, the SPI
I/O signals are set as inputs with weak pull-ups to allow the platform board circuitry to
access the SPI Flash Memory devices.
The SPI Cycle Frequency (SCF) register is configured by the BIOS as follows:
• 000: 20-MHz SPI support
• 001: 33-MHz SPI support
• 001: 33-MHz SPI support
Table 22-1. SPI Signals
Signal Name
Direction/
Type
Description
O
SPI Clock:
The default is 20 MHz, but can be set to 33 MHz. When the
bus is idle, the owner drives the clock signal low.
O
SPI Chip Select 0:
Used as the SPI bus request signal for the first SPI
Flash device.
O
SPI Chip Select 1:
Used as the SPI bus request signal for the second SPI
I
SPI Master IN Slave OUT:
Data input pin
O
SPI Master OUT Slave IN:
Data output pin
Table 22-2. SPI Timings - Typical
Parameter
Value
Description
CS# Setup
30 ns (min.)
CS# Hold
30 ns (min.)
Clock High
22 ns (min.)
Clock Low
22 ns (min.)