Intel C2550 FH8065401488912 Data Sheet
Product codes
FH8065401488912
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
483
Volume 2—Serial Peripheral Interface (SPI)—C2000 Product Family
Serial Flash Device Compatibility Requirements
22.7.2.1
Single-Input, Dual-Output Fast Read
Note:
When the dual-output-fast-read support is enabled the fast-read support must be
enabled as well.
Note:
22.7.2.2
JEDEC ID
Since each Serial Flash device may have unique capabilities and commands, the JEDEC
ID is the necessary mechanism for identifying the device so the uniqueness of the
device is comprehended by the controller (master). The JEDEC ID uses the opcode 9Fh
and a specified implementation and usage model. This JEDEC Standard Manufacturer
and Device ID Read method is defined in Standard JESD21-C, PRN03-NV.
22.7.2.3
Error Correction and Detection
If the first 8 bits specify an opcode which is not supported, the slave does not respond
and wait for the next high-to-low transition on PCU_SPI_CS[1:0]#. The SPI controller
automatically discards 8-bit words that were not completely received upon deassertion
of the signal.
Any other error correction or detection mechanisms must be implemented in the
firmware and/or the software.
Figure 22-4. Dual Output Fast Read Timing
SPI_CS0_B
SPI_CS1_B
SPI_CS1_B
SPI_MOSI
SPI_MISO
SPI_CLK
23
22 21
2
1
0
0
1
2
3
4
5
6
7
8
9
10
29
30
31
Dual Output Fast Read
Opcode = 3Bh
24-bit address
SPI_CS0_B
SPI_CS1_B
SPI_CS1_B
SPI_MOSI
SPI_MISO
SPI_CLK
6
4
2
4
2
0
32
33
34
35
36
37
38
39
Dummy Byte
40
41
42
43
44
45
46
47
0
6
7
5
3
5
3
1
1
7
Read Data
Byte 0
Read Data
Byte 1
6
4
2
4
2
0
0
6
7
5
3
5
3
1
1
7
Read Data
Byte 2
Read Data
Byte 3
48
49
50
51
52
53
54
55
MOSI switches from
input to output