Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

493

The SERIRQ controller supports a serialized IRQ mechanism developed during the 

1990s. One signal line transmits information between the SERIRQ controller and all of 

the peripherals that support serialized interrupts. This signal line is attached to the SoC 

through the 

 pin. The SoC signal is synchronous to the LPC clock and 

follows the sustained, tri-state protocol that is used by the LPC-bus signals.

The serialized IRQ protocol defines phases of this sustained tri-state signaling as the 

following:

• Sample (S) Phase - The 

 signal is driven low.

• Recovery (R) Phase - The 

 signal is driven high.

• Turn-around (T) Phase - The 

 signal is released.

The SoC interrupt controller supports 21 serial interrupts. These represent the 15 ISA 

interrupts (IRQ0 through IRQ1 and IRQ3 through IRQ15), the four PCI interrupts 

(INTA, B, C, D), and the control signals SMI# and IOCHK#. The serialized interrupt 

information is transferred using three types of SERIRQ frames:

• Start Frame - The 

 signal pin driven low by the SoC serialized interrupt 

controller to indicate the start of the IRQ transmission.

• Data Frames - The serialized IRQ information transmitted by peripherals to the SoC 

pin. The serialized interrupt controller supports 21 data frames.

• Stop Frame - The 

 signal pin driven low by the SoC serialized interrupt 

controller to indicate the end of transmission and the next mode of operation.