Intel C2550 FH8065401488912 Data Sheet
Product codes
FH8065401488912
Volume 2—High Precision Event Timer (HPET)—C2000 Product Family
Programming the HPET
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
544
Order Number: 330061-002US
28.4.3
Programming Timer Interrupts
If each timer has a unique interrupt and the timer has been configured for edge-
triggered mode, then no specific steps are required. If configured to level-triggered
mode, then its interrupt must be cleared by the software by writing a 1 back to the bit
position for the interrupt to be cleared.
Interrupts associated with the various timers have several interrupt mapping options.
The software masks GCFG.LRE when reprogramming the HPET interrupt routing to
avoid spurious interrupts.
28.4.3.1
Mapping Option #1: Legacy Option (GCFG.LRE Set)
When LRE is set, T0C.IR and T1C.IR have no impact for timers 0 and 1.
28.4.3.2
Mapping Option #2: Standard Option (GCFG.LRE Cleared)
If a timer is set for the edge-triggered mode, the timers are not shared with any other
interrupts.
28.4.4
Support of S0idle Power-Saving Mechanism
The HPET is active and keeps running during the S0idle state.
Table 28-4. Legacy Routing
Timer
8259
Mapping
I/O
APIC
Mapping
Comment
0
IRQ0
IRQ2
The 8254 PIT interrupt is blocked and does not cause any
interrupts.
1
IRQ8
IRQ8
The RTC interrupt is blocked and does not cause any interrupts.
2
IRQ11
T2C.IRC and
T2C.IR
For I⁄O APIC mapping, the interrupt is mapped to one of the
interrupts indicated by the value of Interrupt Rout Capability
(IRC) of the TC2 register. This is hardwired to indicate support for
I⁄O APIC interrupts IRQ11, 20, 21, 22, and 23. The 5-bit value of
T2C.IR indicates which of the capable interrupts are used.