Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

548

Order Number: 330061-002US

In addition to providing support for ISA compatible interrupts, this interrupt controller 

also supports PCI-based interrupts (PIRQs) by mapping the PCI interrupt onto a 

compatible ISA interrupt line. Each 8259 PIC supports eight interrupts, numbered 0–7. 

 shows how the controllers are connected.

The SoC does not provide external PIRQ# signal pins. The PIRQs referred to in this 

chapter originate from the SoC internal interrupt-routing unit.

How PIRQA, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, and PIRQH, are routed to 

IRQ0

Master IRQ0

• HPET Timer 0 (if GCFG.LRE is set)
• 8254 Timer (if GCFG.LRE is not set)

1

IRQ1

Master IRQ1

• SERIRQ (1)

IRQ2

Master IRQ2

INTR output of the slave 8259 PIC

1, 2

IRQ3

Master IRQ3

• SERIRQ (3), or
• UART  COM2,  or
• PIRQx

3

IRQ4

Master IRQ4

• SERIRQ (4), or
• UART  COM1,  or
• PIRQx

3

IRQ5

Master IRQ5

• SERIRQ (5), or
• GPIO,  or
• PIRQx

3

IRQ6

Master IRQ6

• SERIRQ (6), or
• GPIO,  or
• PIRQx

3

IRQ7

Master IRQ7

• SERIRQ (7), or
• GPIO,  or
• PIRQx

3

IRQ8

Slave IRQ0

• HPET Timer 1 (if GCFG.LRE is set)
• RTC (if GCFG.LRE is not set)

1

IRQ9

Slave IRQ1

• SERIRQ (9), or
• PIRQx,  or
• From SCI (based on the ACTL.SCIS and PM1_CNT.SCI_EN 

registers)

3

IRQ10

Slave IRQ2

• SERIRQ (10), or
• PIRQx,  or
• From SCI (based on the ACTL.SCIS and PM1_CNT.SCI_EN 

registers)

3

IRQ11

Slave IRQ3

• SERIRQ (11), or
• HPET  Timer  2,  or
• PIRQx,  or
• From SCI (based on the ACTL.SCIS and PM1_CNT.SCI_EN 

registers)

3

IRQ12

Slave IRQ4

• SERIRQ (12), or
• PIRQx

3