Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 3 of 3

Order Number: 330061-002US

583

DDR3_1_BS[2:0]

O

DDR

3

VDDR

DDR3 Bank Select: Defines 

which banks are being 

addressed within each rank. 

BA0 - BA2 define to which 

bank an Active, Read, Write or 

Pre-charge command is being 

applied (for 256 MB and 512 

MB, BA2 is not applied). The 

Bank address also determines 

if the mode register or one of 

the extended mode registers 

is to be accessed during an 

MRS or EMRS command cycle.

DDR3_1_DQPU

I/O

DDR

1

VDDR

DDR3 Compensation Pad. 

Board trace + External 

Precision resistor = 35. The 

resistor is pulled-down to 

VSS.

DDR3_1_CMDPU

I/O

DDR

1

VDDR

DDR3 Compensation Pad. 

Board trace + External 

Precision resistor = 24 or 33.5 

depending on target RON. The 

resistor is pulled-down to 

VSS.

DDR3_1_MON1P

I/O

DDR

1

VDDR

DDR3 PLL Monitor Port1.

DDR3_1_MON1N

I/O

DDR

1

VDDR

DDR3 PLL Monitor Port1.

DDR3_1_MON2P

I/O

DDR

1

VDDR

DDR3 PLL Monitor Port2.

DDR3_1_MON2N

I/O

DDR

1

VDDR

DDR3 PLL Monitor Port2.

DDR3_1_REFP

I

DDR

1

VDDR

DDRIO MPLL Input Reference 

Clock.

• For SKU 8, this input is 

connected to VSS on the 

platform board.

DDR3_1_REFN

I

DDR

1

VDDR

DDRIO MPLL Input Reference 

Clock.

• For SKU 8, this input is 

connected to VSS on the 

platform board.

DDR3_1_DQECC[7:0]

I/O

DDR

8

VDDR

DDR3 ECC Bus: Memory Error 

Correction Code driven along 

with read and write data.

TOTAL

145