Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 3 of 3

Order Number: 330061-002US

631

This chapter contains information that is subject to change.

This chapter is organized by signal interface. Each sub-chapter contains the interface 

DC, AC, and signal timing requirements and characteristics. Some of these 

requirements and characteristics are base on industry and Intel standards. When the 

SoC interface complies to a standard, the reader is referred to the standard for the 

requirements and characteristics. SoC exceptions to the standard, if any, are shown as 

well as any of the standard’s optional interface characteristics as implemented by the 

SoC design.

Most of the information presented here is in Table and Figure form. In some cases, the 

reader is referred to one of the functional-description chapters where additional 

interface-related information is available.

The DC and AC characteristics of the SoC DDR3 memory interface allow it to interface 

to and control SDRAM components complying to the DDR3 SDRAM Specification 

JESD79-3E. Both single-ended and differential signals are covered in the specification. 

Refer to the specification’s sections:

• JESD79-3E, Section 8 - AC and DC Input Measurement Levels
• JESD79-3E, Section 9 - AC and DC Output Measurement Levels

The key DC and AC parameters for the SoC DDR3 memory controllers are shown in 

, 

, 

.

I

IL

Input Leakage Current

-

20

-

uA

10

V

IL

Input Low Voltage

-

-

SMREF - 

0.125

V

2,  3

V

IH

Input High Voltage

SMREF + 

0.125

-

-

V

2, 4, 

5

R

ON

DDR3L Data Buffer On Resistance

26

-

40

Ω

6

V

OL

Output Low Voltage

-

(VDDQ/2)* 

(R

ON

 / 

(R

ON

+R

VTT_

TERM

))

-

V

2,  7