Intel C2550 FH8065401488912 Data Sheet
Product codes
FH8065401488912
Volume 3—Signal Electrical and Timing Characteristics—C2000 Product Family
General Clocks Provided by SoC Interfaces
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 3 of 3
September 2014
676
Order Number: 330061-002US
33.17.2
Interface Timing Parameters and Waveforms
contain the timing specifications for the PMU_SUSCLK
signal.
Notes:
1.
In
, V
TL
is 20% of V3P3A and V
TH
is 80% of V3P3A.
2.
Cycle to cycle.
Notes:
1.
In
, V
TL
is 20% of V3P3A and V
TH
is 80% of V3P3A.
2.
Cycle to cycle.
Table 33-35. SUS Clock (RTC Clock) Output Signal Timing Specifications
Symbol
Parameter
Min
Typ
Max
Units
Fig
Notes
Operating frequency
–
32.768
–
kHz
Tolerance
100
–
100
ppm
Duty Cycle
40
–
60
%
T
SLF
Slew Rate - Falling
Edge of Clock
5
–
10
ns
1
T
SLR
Slew Rate - Rising Edge
of Clock
5
–
10
ns
1
Jitter
300
–
300
ps
2
T
VAL
PMU_SUSCLK SoC
output stable after
platform board de-
asserts RSMRST_B
100
–
–
ms
Figure 33-15.SUS Clock (RTC Clock) Valid Timing Diagram
Table 33-36. Flex Clock Output Signal Timing Specifications
Symbol
Parameter
Min
Typ
Max
Units
Fig
Notes
Operating frequency
–
25
–
MHz
25 MHz Mode
Operating frequency
–
33
–
MHz
33 MHz Mode
Tolerance
100
–
100
ppm
Duty Cycle
40
–
60
%
T
SLF
Slew Rate - Falling
Edge of Clock
1
–
50
ns
1
T
SLR
Slew Rate - Rising Edge
of Clock
1
–
50
ns
1
Jitter
300
–
300
ps
2
SoC input:
RSMRST_B
SoC output:
PMU_SUSCLK
T
VAL
valid