Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

77

IA32_MCG_STATUS

A 64-bit, read-only MSR determines the current state of the machine check 

architecture of the SoC after an error has occurred. The SoC hardware sets and clears 

these bits. Only three bits are defined:

• Bits [63:3] = Reserved.
• Bit 2 = MCIP - Machine Check In Progress flag. This bit is set when the execution of 

the SoC machine check handler begins and can be cleared by the software. If 

another machine check exception is signaled while this bit is set, the machine 

enters the shutdown state.

• Bit 1 = EIPV - Error IP Valid flag. This flag is always 0 for the SoC indicating that 

the Instruction Pointer (IP) pushed onto the stack does not necessarily point to the 

instruction that caused the exception.

• Bit 0 = RIPV - Restart IP Valid flag. Restart is never possible with the SoC, and so 

this bit is always 0.

The SoC does not provide this 64-bit MSR. The Control MSR Present (MCG_CTL_P) flag 

of the IA32_MCG_CAP (MSR 179h) is 0 indicating that the IA32_MCG_CTL register is 

not present.

The SoC has six sets of machine check error-reporting MSR banks that reside at MSR 

addresses 400h through 416h. See 

. These 64-bit registers are described in 

this section.

A shaded cell means that the MSR register is not implemented for the particular 

machine check bank. The physical portions of the SoC are shown in 

Figure 4-5

.

CMP

BIU

MC0

0x400

0x401

x402

CMP

BIU

MC1

1

1. The MC1 bank is provided for compatibility with existing operating systems. While the name MC1 is mentioned here, the RMSR

instructions to MC1 are ignored and the RMSR instruction never reports errors nor has any enable bits.

0x404

0x405

CMP

L2

MC2

0x408

0x409

0x40A

Core

MEC

MC3

0x40C

0x40D

0x40E

Core

FEC

MC4

0x410

0x411

0x412

Uncore

SSA

MC5

0x414

0x415

0x416