Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

95

A System Error (SERR) is generated by an SoC logic block to indicate a condition of 

serious system instability. The SERR events are mapped to an NMI or SMI at the SoC 

level.

This section describes local and global error logging. The log registers are named 

xxxxFERR and xxxxNERR where xxxx varies. First and next errors are captured at both 

the local level (correctable and uncorrectable) and the global level (correctable, 

non-fatal, and fatal). PCIe specifies its own error-logging mechanism which is not 

described here. Refer to the PCI Express Base Specification, Revision 2.1 for details.

Once the first error and the next error have been indicated and logged, the log 

registers for that error remains valid until either:

• The First Error bit is clear in the associated error status register, or
• The SoC generates the power-good, platform reset (PMU_PLTRST_B output pin).

The software clears an error bit by writing 1 to the corresponding bit position in the 

error status register.

1. The first error event is indicated by setting the corresponding bit in the FERR status 

2. If the same error occurs before the FERR status register bit is cleared, the error is 

3. In the case of simultaneous multiple errors with same severity, any two errors are 

4. Updates to the error status and error log registers appear atomic to the software.
5. Once the first error information is logged in the FERR log register, the logging of the 

6. The error status registers, the error mask registers, and the error log registers are 

cleared by the power-on reset only. The contents of error log registers are 

preserved across a reset (while the power-good COREPWROK input pin remains 

asserted).