Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

115

Global interrupt handling is described in this chapter. The types of interrupts are 

described as well as the routing and mapping of these interrupts to the integrated I/O 

Advanced Programmable Interrupt Controller (APIC) and 8259 Programmable Interrupt 

Controller (PIC).

The SoC does not provide external INTA# through INTD# PCI interrupt signal pins. The 

PCI Express* integrated endpoints and the PCIe* interrupt messages internally 

produce the equivalent of these four interrupt signals for each device. For each of the 

possible 32 PCI devices, each of these four interrupt signals can be programmed to be 

routed to one of eight internal interrupt signals called PIRQA# through PIRQH#. For a 

diagram of the routing scheme, see 

PIRQA#

If REN bit = 0,

to 1 of 11 IRQx 

of 8259 PIC

to 8259 PIC

to APIC

PIRQC#

If REN bit = 0,

to 1 of 11 IRQx 

of 8259 PIC

to 8259 PIC

to APIC

PIRQD#

If REN bit = 0,

to 1 of 11 IRQx 

of 8259 PIC

to 8259 PIC

to APIC

PIRQE#

If REN bit = 0,

to 1 of 11 IRQx 

of 8259 PIC

to 8259 PIC

to APIC

PIRQF#

If REN bit = 0,

to 1 of 11 IRQx 

of 8259 PIC

to 8259 PIC

to APIC

PIRQG#

If REN bit = 0,

to 1 of 11 IRQx 

of 8259 PIC

to 8259 PIC

to APIC

PIRQH#

If REN bit = 0,

to 1 of 11 IRQx 

of 8259 PIC

to 8259 PIC

to APIC

PIRQB#

If REN bit = 0,

to 1 of 11 IRQx 

of 8259 PIC

to 8259 PIC

to APIC

PIRQA through PIRQH

Routing Control Registers

PCI Dev 0-31 Interrupt

Routing Registers

INTA#
INTB#
INTC#

INTD#

PCI 

Dev 

31

to 1 of 8 

PIRQx#

INTA#
INTB#
INTC#

INTD#

PCI 

Dev 0

to 1 of 8 

PIRQx#

IR31 Register

IR0 Register

Total of

32 Devices

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