Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

118

Order Number: 330061-002US

NMI is generated by serious system events, memory parity errors, some System Errors 

(SERR), and PCI Express fatal errors.

The SoC provides an external input signal pin (

) and is detected on the rising edge. 

The 

 is reset by the software by setting the corresponding 

 source enable/

disable bit in the 

The 

 is broadcast to all cores in the SoC. Sleeping cores are first awakened.

The SoC provides interrupt mapping to generate the 

 for various SoC and system 

events. More information is provided in 

The SMI indicates any of the several system-level conditions. Examples are:

• Thermal-sensor events
• Throttling activation
• System management RAM access
• Chassis open
• System power button pressed
• System Management Bus (SMBus) events
• Power  Management  Events  (PME)
• PCI Express Hot-Plug* events (Hot-Plug events are not supported by the SoC.)
• Real Time Clock (RTC) alarm activation
• Various system-state-related activities

An SMI causes the system to enter System Management Mode (SMM). SMM is an 

operating mode in which all normal execution, including the operating system, is 

suspended, and special, separate software, usually firmware or a hardware-assisted 

debugger, is executed in high-privilege mode. The SMI is broadcast to all cores in the 

SoC. Sleeping cores are first awakened.

Various events can be programmed to generate either a System Control Interrupt (SCI) 

or as an SMI. Mapping events to SMI can be used when a legacy (APM) OS is in use. 

The SCI Enable (SCI_EN) bit of the Power Management 1 Control (PM1_CNT) register 

controls whether the event is routed as an SCI or an SMI. The PM1_CNT register is 

located in the I/O space at ACPI_BASE_ADDRESS, offset 4.