Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

122

Order Number: 330061-002US

The interrupts that can be routed to the input of the integrated 8259 PIC are shown in 

. The 8259 PIC registers are described in 

 

1.

Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8#.

2.

The slave 8259 controller is cascaded onto the master 8259 controller through the master controller 

interrupt input IRQ2.

3.

For routing of the PIRQA through PIRQH Interrupts, see 

IRQ0

Master IRQ0

HPET Timer 0 (if GCFG.LRE is set)

8254 Timer (if GCFG.LRE is not set)

1

IRQ1

Master IRQ1

SERIRQ (1), or

IRQ2

Master IRQ2

INTR output of the Slave 8259 PIC

1, 2

IRQ3

Master IRQ3

SERIRQ (3), or

UART COM2, or

PIRQx

3

IRQ4

Master IRQ4

SERIRQ (4), or

UART COM1, or

PIRQx

3

IRQ5

Master IRQ5

SERIRQ (5), or

GPIO, or

PIRQx

3

IRQ6

Master IRQ6

SERIRQ (6), or

PIRQx

3

IRQ7

Master IRQ7

SERIRQ (7), or

PIRQx

3

IRQ8

Slave IRQ0

HPET Timer 1 (if GCFG.LRE is set)

RTC (if GCFG.LRE is not set)

1

IRQ9

Slave IRQ1

SERIRQ (9), or

PIRQx, or

from SCI (based on ACTL.SCIS and PM1_CNT.SCI_EN registers)

3

IRQ10

Slave IRQ2

SERIRQ (10), or

PIRQx, or

from SCI (based on ACTL.SCIS and PM1_CNT.SCI_EN registers)

3

IRQ11

Slave IRQ3

SERIRQ (11), or

HPET Timer 2, or

PIRQx, or

from SCI (based on ACTL.SCIS and PM1_CNT.SCI_EN registers)

3

IRQ12

Slave IRQ4

SERIRQ (12), or

PIRQx

3

IRQ13

Slave IRQ5

The interrupt (floating point error) is not supported.

IRQ14

Slave IRQ6

SERIRQ (14), or

IRQ15 from ISA IDE Interrupt, or

PIRQx

3

IRQ15

Slave IRQ7

SERIRQ (15), or

PIRQx

3