Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

125

This chapter describes the platform board and SoC power-management signal 

interchange, SoC power-source sequencing requirements, and reset signaling for the 

various power states. The information is meant for platform-board designers. The SoC 

only supports the G3 (Mechanical Off) with or without an RTC coin-cell battery, S5 (Soft 

Off), and S0 (Fully On) states. The ACPI Sleep States (S1, S2, S3, S4) are not 

supported.

If the platform board provides a functional coin-cell battery for the SoC integrated Real 

Time Clock (RTC), the RTC power well of the SoC is functional during the G3 state. The 

voltage is supplied to the SoC by VCCRTC_3P3 (pin AG42).

When a coin-cell battery of sufficient voltage is inserted while in the G3 state, the 

platform board signals the SoC that the RTC power well voltage has been valid for a 

sufficient period of time for the SoC to clear its RTC registers. It does this by 

deasserting the RTC well RTEST_B and SRTCRST_B. See 

. 

When the SRTCRST_B signal is deasserted, it indicates the end of RTC reset. When 

deasserted, RTEST_B signal indicates the RTC battery is producing a valid voltage. 

When a logic low, RTEST_B indicates a weak or missing RTC battery. The SoC makes 

the state of this RTEST_B signal accessible to software to detect a weak or missing RTC 

battery.

If the platform board does not have a functioning coin-cell battery, the SoC RTC power 

well ramps up the same time as V3P3A during the standby power-up sequence 

described in the following subsection. What occurs before that time is shown in 

.

When no power other than the coin-cell battery is supplied to the SoC and when the 

active-low RTEST_B and SRTCRST_B SoC input signals are both logic-high levels 

(deasserted), it indicates that the SoC is provided what it needs to keep the RTC 

circuitry functioning during the G3 state. Unless they were set to their default values by 

an active-low signal on RTC well RTEST_B or SRTCRST_B, register bits located in the 

RTC well that were set/cleared while the SoC was previously in the S0 or S5 state are 

preserved by the SoC. These preserved register bits affect how the SoC reacts to future 

power events and its future power-state transitions.

The next subsection begins to describe the sequence for the case where the RTC-well 

register bits are at their default values (after the assertion of the RTEST_B SoC input 

signal by the platform board). This is refer to as “powering-up for the first time.” The 

SoC power-management mechanism has the capability of determining and 

remembering the first power-up situation.

If the platform board does not have an RTC coin battery or if the RTC battery voltage is 

not valid, the SoC is always in a “powering-up for the first time” situation as it 

transitions from the G3 state to the S5 state.