Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

141

The SoC can initiate a power-down to S5 sequence while in the S0 (Working) state. The 

situations when this occurs are shown as Reset Types 3 and 5 in 

.

Reset Type 3 is an orderly transition to S5. Reset Type 5 is a quick transition to S5 and 

usually caused by some kind of unexpected time out condition but actually appears like 

a Type-3 reset to the platform board.

The sequence from S0 to S5 is the same as sequence steps 1 through 8 shown 

. Refer to 

 and 

.

The SoC remains in the S5 state until a Wake Event occurs. Wake Event hardware is 

powered by the SUS well and RTC well power which remain powered-on during S5.

When sleeping in the S5 state, the SoC transitions to either the S0 (Fully-On) or the G3 

(Mechanical-Off) state when certain configured Wake Events occur. S5 transitions to G3 

are always initiated by the platform board via the RSMRST_B signal. The Wake Events 

are shown in 

.

While the SoC is in the S5 state, the active-low SoC output signal PMU_SLP_S45_B 

remains asserted.

See 

 for sequences when 

powering up from the G3 state with an active After G3 Enable (AG3E) register bit or 

with the SoC AG3E hard strap active.

When a configured Wake Event occurs while the SoC is sleeping in the S5 state, the 

SoC exits the S5 state, and deasserts the active-low SoC output signal 

PMU_SLP_S45_B. This is an indication to the platform board to begin powering-up the 

DDR3 voltages and the SoC Core well voltages. See 

 for the 

signal and power-rail sequences and timing parameters.