Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
157
Volume 2—Power Management—C2000 Product Family
Serial Voltage Identification (sVID) Controller
9.6
Serial Voltage Identification (sVID) Controller
The sVID controller consists of three signal pins and is defined in the VR12/IMVP7 Pulse
Width Modulation, Revision 1.61. The three signals provided by the SoC are in
9.6.1
SVID VR Requirements
It is required that the voltage rails for the cores (VCC) and fabric (VNN) support IMON
as defined by the VR12/IMVP7 SVID protocol specification.
9.6.1.1
SVID Controller Addressing Requirements
The following address assignments are required. This definition supersedes any
definitions defined in the VR12/IMVP7 Pulse Width Modulation, Revision 1.61
specification.
SoC Power Management expects VR addresses to always be sequential with no gaps in
address assignments for any Voltage Rails.
9.6.2
Command Byte Encoding
Refer to VR12/IMVP7 SVID Protocol, Revision 1.5 for protocol details.
9.6.2.1
sVID Commands
The sVID commands are shown in
. The send payload VID values are shown in
the
Table 9-4.
SVID Controller Addressing Requirements
Rail
Address[3:0]
Definition
VCC
0h
CPU Core rail
VNN
1h
SoC rail
VDDR_A
2h
DDR Channel A (only if VID is used on platform). Soft strap must be set to
indicate whether rail is present. See
VDDR_B
3h
DDR Channel B (only if VID is used on platform). Soft strap must be set to
indicate whether rail is present. See