Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
191
Volume 2—Gigabit Ethernet (GbE) Controller—C2000 Product Family
Signal Descriptions
11.4
Signal Descriptions
The signal description table has the following headings:
• Signal Name: The signal/pin name
• Direction: The buffer direction is either input, output, or I/O (bi-directional)
• Type: The buffer type found in
• Direction: The buffer direction is either input, output, or I/O (bi-directional)
• Type: The buffer type found in
• Description: A brief explanation of the signal function
Table 11-1. Signals (Sheet 1 of 3)
Signal Name
Direction/
Type
Description
O
SerDes/SGMII Serial Data Output Port
: Differential SGMII/
SerDes transmit interface.
O
SerDes/SGMII Serial Data Output Port
: Differential SGMII/
SerDes transmit interface.
I
SerDes/SGMII Serial Data Input Port
: Differential SGMII/
SerDes receive interface.
I
SerDes/SGMII Serial Data Input Port
: Differential SGMII/
SerDes receive interface.
I
GbE 100-MHz differential clock
with 100 ppm maximum jitter.
External SerDes/SGMII differential 100-MHz reference clock from
an external generator. This clock must be powered from the
Suspend (SUS) power well. When the device is enabled for the
2.5-GbE operation, the standard 100-MHz reference clock must be
replaced with a 125-MHz reference clock.
O
Observability port
. In normal operation, configure as
GBE_RCOMP.
O
GbE EEPROM Data Input:
Data is output to EEPROM. If all four
LAN Ports are disabled via soft straps, this signal can be used as
GPIO SUS Port 13.
I
GbE EEPROM Data Output
: Data is input from EEPROM. If all
four LAN Ports are disabled via soft straps, this signal can be used
as GPIO SUS Port 14.
O
GbE EEPROM Serial Clock:
Serial clock output to EEPROM
Operates at ~2 MHz. If all four LAN Ports are disabled via soft
straps, this signal can be used as GPIO SUS Port 15.
O
GbE EEPROM Chip Select
: Chip select Output to EEPROM. If all
four LAN Ports are disabled via soft straps, this signal can be used
as GPIO SUS Port 16.
I/O, OD
GbE SMBus Clock
: One clock pulse is generated for each data bit
transferred. An external pull- down of 10K resistor is required.
Resistor value should be calculated based on the bus load. (Refer
to the Platform Design Guide.)
If the GBE_SMBD interface is not used, the signals can be used as
NCSI_TX_EN transmit enable (input).
Note:
If not used, should have an external pull-down resistor.
I/O, OD
GbE SMBus Clock
: One clock pulse is generated for each data bit
transferred. An external pull-up resistor is required.
If the SMBus interface is not used, the signals can be used as the
If the SMBus interface is not used, the signals can be used as the
NCSI_CLK_IN signal.
As an input signal, the NCSI_CLK_IN must be connected to the 50-
As an input signal, the NCSI_CLK_IN must be connected to the 50-
MHz NC-SI REF_CLK generator on the platform board.
This same signal pin can be programmed to provide the 50-MHz
This same signal pin can be programmed to provide the 50-MHz
NC-SI REF_CLK for the NC-SI devices on the platform board
including the SoC. If so programmed, the NCSI_CLK_IN pin also
functions as the “NCSI_CLK_OUT” of the SoC.
Note:
If this pin is not used, it must be connected to an external
pull-down resistor.