Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

225

Reset Warn is an internal SoC indication to the PCIe Root Port controllers. The SoC 

ensures a number of conditions are met before applying the reset.

The root ports comply with the PCI Bus Power Management Interface Specification, 

Revision 1.2. Refer to the specification for details of the Root Port PCI Power 

Management Capabilities and register descriptions.

The PCI Express Root Ports support the D0 and D3 states (both D3

HOT

 and D3

COLD

).

The PCI-PM D0, D3

HOT

, D3

COLD

 states correspond to PCI Express link states L0, L1, 

and L3. When all the PCIe ports and the IOAPIC are programmed to the D3

HOT

 state, 

the upstream link automatically transitions to the link state L1. The SoC also supports 

the PME_Turn_Off/PME_TO_Ack PCIe message handshake protocol to enter the 

D3

COLD

/L3 device/link states.

Each function (downstream ports) behaves as follows when in the D3

HOT

 state:

• The function responds to configuration cycles from upstream.
• The function does not respond to memory cycles from upstream except for 

Completions.

• The function does not respond to upstream I/O cycles except for completions.The 

function does not initiate upstream transactions.

• The functions does not reset its registers when programmed from D0 to D3

HOT.