Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

240

Order Number: 330061-002US

The PCI Express Root Ports support forwarding poisoned information between the 

coherent interface and the PCIe link, and vice-versa. Also, forwarding poisoned data 

between peer PCIe ports is supported. The PCIe has a mode where poisoned data is 

never sent out on PCI Express, i.e., any packet with poisoned data is dropped internally 

in the root port and an error escalation done.

The PCIe links are 32-bit CRC protected providing for high reliability. The Data Link 

Layer Packets (DLLPs) utilize a 16-bit CRC scheme. PCIe also provides for a software-

transparent recovery from temporary link failures. When received packets are in error, 

the hardware automatically retransmits the packet.

This also refers to as Dynamic Link Width (DLW) Reduction.

The Root Port PCI Express interface provides a mechanism to recover from a failed link. 

PCI Express link can operate in a different link width. The SoC supports PCIe port 

operation in x8, x4, x2, and, in special cases, x1. In case of a persistent link failure, the 

PCIe link falls back to a smaller link width in attempt to recover from the error. A PCIe 

x8 link falls back to a x4 link. A PCIe x4 falls back to x2 link, and then to X1 link. This 

mechanism enables continuation of system operation in case of PCIe link failures.

If the SoC receives a legitimate PCIe-defined packet that is not included in PCIe 

supported transactions, then the SoC treats that packet as an unsupported transaction 

and follows the PCIe rules for handling unsupported requests. If the SoC receives a 

completion with a requester ID set to the Root Port Requester ID and no matching 

request is outstanding, then this is considered an unexpected completion. 

Also, the SoC detects malformed packets from PCI Express and reports them as errors 

per the PCI Express Specification rules. If the SoC receives a Type 0 Intel-

Vendor_Defined message that terminates at the root complex and if the SoC does not 

recognize this as a valid Intel-supported message, the message is handled by the SoC 

as an unsupported request with appropriate error escalation (as defined in PCI Express 

Specification). For Type 1 Vendor_Defined messages which terminate at the root 

complex, the SoC discards the message with no further action.

If the local CPU transaction targets a PCIe link that is not connected to any device or 

the link is down (DL_Down status), the SoC treats that as a master abort situation. This 

is required for PCI bus scans to non-existent devices to go through without creating 

any other side effects. If the transaction is non-posted, the SoC synthesizes an 

unsupported request response status (if non-posted) back to local CPU targeting the 

unconnected link or returns all Fs on reads and a successful completion on writes 

targeting the down link. 

Accesses by the local CPU to the root port registers.