Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
257
Volume 2—SATA Controllers (SATA2, SATA3)—C2000 Product Family
PCI Configuration Registers
13.5
PCI Configuration Registers
All of the SATA configuration registers are in the core well. All registers not mentioned
are reserved.
All configuration registers are reset by Function Level Reset (FLR) unless specified
otherwise explicitly.
Table 13-6. Summary of PCI Configuration Registers—0x_00_13_00 (Sheet 1 of 2)
Offset Start
Offset End
Register ID—Description
0h
3h
“ID (ID)—Offset 0h”
4h
5h
“CMD (CMD)—Offset 4h”
6h
7h
“STS (STS)—Offset 6h”
8h
8h
“RID (RID)—Offset 8h”
9h
9h
“PI (PI)—Offset 9h”
Ah
Bh
“CC (CC)—Offset Ah”
Ch
Ch
“CLS (CLS)—Offset Ch”
Dh
Dh
“MLT (MLT)—Offset Dh”
Eh
Eh
“HTYPE (HTYPE)—Offset Eh”
10h
13h
“PCMDBA (PCMDBA)—Offset 10h”
14h
17h
“PCTLBA (PCTLBA)—Offset 14h”
18h
1Bh
“SCMDBA (SCMDBA)—Offset 18h”
1Ch
1Fh
“SCTLBA (SCTLBA)—Offset 1Ch”
20h
23h
“LBAR (LBAR)—Offset 20h”
24h
27h
“ABAR (ABAR)—Offset 24h”
2Ch
2Fh
“SS (SS)—Offset 2Ch”
34h
34h
“CAP (CAP)—Offset 34h”
3Ch
3Fh
“INTR (INTR)—Offset 3Ch”
40h
41h
“PTIM (PTIM)—Offset 40h”
42h
43h
“STIM (STIM)—Offset 42h”
44h
44h
“D1TIM (D1TIM)—Offset 44h”
48h
48h
“Synchronous_DMA_Control (Synchronous_DMA_Control)—Offset 48h”
4Ah
4Bh
“Synchronous_DMA_Timing (Synchronous_DMA_Timing)—Offset 4Ah”
54h
57h
“IIOC (IIOC)—Offset 54h”
70h
71h
“PID (PID)—Offset 70h”
72h
73h
“PC (PC)—Offset 72h”
74h
75h
“PMCS (PMCS)—Offset 74h”
80h
81h
“MID (MID)—Offset 80h”
82h
83h
“MC (MC)—Offset 82h”
84h
87h
“MA (MA)—Offset 84h”
88h
89h
“MD (MD)—Offset 88h”
90h
91h
“MAP (MAP)—Offset 90h”
92h
93h
“PCS (PCS)—Offset 92h”
94h
97h
“TM (TM)—Offset 94h”
98h
9Bh
“TM2 (TM2)—Offset 98h”