Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 2—SATA Controllers (SATA2, SATA3)—C2000 Product Family
Memory-Mapped Registers
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
260
Order Number: 330061-002US
13.8
Memory-Mapped Registers
All of the AHCI memory-mapped registers are in the core well unless stated otherwise.
The memory-mapped registers within the SATA controller exist in non-cacheable
memory space. Additionally, locked accesses are not supported. If the software
attempts to perform locked transactions to the registers, indeterminate results occur.
Register accesses have a maximum size of 64 bits. The 64-bit accesses must not cross
an 8-byte alignment boundary.
The registers are divided into two sections – global control registers and port control
registers. All registers that start below address 100h are global and meant to apply to
the entire HBA. The port control registers are the same for all ports, and there are as
many registers banks as there are ports.
All registers not defined and all reserved bits within registers return 0 when read.
These registers are not accessible when CC.SCC is 01h.
All memory registers are reset by FLR unless specified otherwise.
Note:
The memory map registers below are for SATA port 0 and 1 for both SATA2 and SATA3
controllers. Memory map register information for ports 2 and 3 for the SATA2 controller
are identical to ports 0 and 1. Register offset information is added in the later revisions.
Table 13-9. Summary of Memory-Mapped I/O Registers—ABAR (Sheet 1 of 2)
Offset Start
Offset End
Register ID—Description
0h
3h
“GHC_CAP (GHC_CAP)—Offset 0h”
4h
7h
“GHC (GHC)—Offset 4h”
8h
Bh
“IS (IS)—Offset 8h”
Ch
Fh
“GHC_PI (GHC_PI)—Offset Ch”
10h
13h
“VS (VS)—Offset 10h”
1Ch
1Fh
“EM_LOC (EM_LOC)—Offset 1Ch”
20h
23h
“EM_CTL (EM_CTL)—Offset 20h”
24h
27h
“GHC_CAP2 (GHC_CAP2)—Offset 24h”
A0h
A3h
“VSP (VSP)—Offset A0h”
A4h
A7h
“VS_CAP (VS_CAP)—Offset A4h”
C4h
C5h
“PFB (PFB)—Offset C4h”
C8h
C9h
“SFM (SFM)—Offset C8h”
100h
103h
“PxCLB (PxCLB0)—Offset 100h”
104h
107h
“PxCLBU (PxCLBU0)—Offset 104h”
108h
10Bh
“PxFB (PxFB0)—Offset 108h”
10Ch
10Fh
“PxFBU (PxFBU0)—Offset 10Ch”
110h
113h
“PxIS (PxIS0)—Offset 110h”
114h
117h
“PxIE (PxIE0)—Offset 114h”
118h
11Bh
“PxCMD (PxCMD0)—Offset 118h”
120h
123h
“PxTFD (PxTFD0)—Offset 120h”
124h
127h
“PxSIG (PxSIG0)—Offset 124h”
128h
12Bh
“PxSSTS (PxSSTS0)—Offset 128h”
12Ch
12Fh
“PxSCTL (PxSCTL0)—Offset 12Ch”
130h
133h
“PxSERR (PxSERR0)—Offset 130h”