Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

288

Order Number: 330061-002US

The SMBus Message Transport (SMT) controller has three regions in Configuration 

Space. These are discovered by software in the configuration space as bus 0, device 

19 (decimal), function (0). The address offsets and capability IDs of the contents of 

these regions are:

1. PCI Standard Header

— Type  0

2. PCI Capabilities List

— 40h: PCI Express* - Capability ID = 10h
— 80h: PCI Power Management - Capability ID = 01h
— 8Ch: Message Signaled Interrupts (MSI) - Capability ID = 05h
— Various implementation-specific and Intel-reserved registers

3. PCI Express Extended Capabilities List

— 100h: Advanced Error Reporting (AER) - Extended Capability ID = 0001h

The SMT controller operation is DMA-based in which descriptors and data are 

exchanged between the SoC hardware and the firmware through system memory. This 

DMA mode is available for the SMT acting both as master and target.

As transport layer functionality, SMT transfers messages between the devices on the 

SMBus segment (to which it is physically connected) and the SoC firmware. The SMT 

hardware is physically located within the SoC and resides within its PCIe space. In the 

PCIe hierarchy, SMT is bus 0, device 19 (decimal), function 0.