Intel C2518 FH8065501516710 Data Sheet

Product codes
FH8065501516710
Page of 746
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Controller Characteristics and Operation
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
298
Order Number: 330061-002US
The hardware will ACK all valid transactions above. An exception is when processing 
the Assign Address protocol, if the received UDID does not match any internal UDID 
the hardware begins NACKing after the first unmatched byte. Another exception is that 
if the Address Resolved flag is asserted and a Get UDID (general) command is received, 
the command byte is NACKed. Finally, a PEC failure causes a transaction to be NACKed.
In both directed protocols, Get UDID (directed) and Reset Device (directed), the 
second byte, or ARP command byte, consists of the target slave address with an 
appended 0 or 1 to denote a Reset Device or Get UDID protocol, respectively. 
Therefore, the hardware uses address bits [7:1] for address comparison and LSB bit 0 
to determine the protocol.
Since the SMT supports multiple UDIDs, during the ARP process it participates in the 
Get UDID (general) and Assign Address protocols once for each UDID such that each 
UDID has a slave address which is resolved by the ARP master.
For GPBR and all both Get UDID flavors, the transaction is descriptor-only with no 
target data written to memory, and the descriptor is managed by the hardware.
Note:
The firmware implements a time-out mechanism such that if the SoC issues the Notify 
ARP Master command and the ARP Master does not respond within a particular time 
period then the SoC re-issues the Notify ARP Master command. It is implemented to 
comply with SMBus 2.0 Specification for bus timing.
Table 15-9. Hardware/Firmware Response to SMBus and ARP Protocols
Received
ARP Protocol
AV 
Flag
AR 
Flag
ARP
States 
(1-8,...)
SoC Hardware and Firmware
Response
Ordinary SMBus protocol
Ordinary SMBus protocol
T
n/a
9,10,11
Normal hardware-firmware flow
SMBus block-read
T
n/a
9,10,11
The hardware returns the specified number of bytes 
from the hardware buffers.
ARP protocol
Prepare to ARP 
n/a
n/a
12,13
Normal hardware-firmware flow
Reset Device (general)
n/a
n/a
12,14,15
Normal hardware-firmware flow
Assign Address
n/a
n/a
12,14,16,
17,18
Normal hardware-firmware flow
Get UDID (general)
n/a
T
12,14,16,
19,21
The hardware does NACK the ARP command byte to 
indicate it has a valid assigned slave address (ARP is 
complete).
Get UDID (general)
T
F
12,14,16,
19,21,22,
23,24
The hardware returns its UDID and corresponding 
Slave Address.
Get UDID (general)
F
F
12,14,16,
19,21,22,
23,25
The hardware returns its UDID and 0xFF for its 
address.
Reset Device (directed)
T
n/a
12,14,15,
19,20,26,
15
Normal hardware-firmware flow
Get UDID (directed)
T
n/a
12,14,16,
19,20,26,
27,29
The hardware returns its UDID and corresponding 
Slave Address.
None of the above ARP 
protocols
n/a
n/a
12,14,16,
19,20,26,
27,28
Normal hardware-firmware flow
(error handling situation)