Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

314

Order Number: 330061-002US

All master transactions on the physical SMBus pins use descriptors. The high-level flow 

typically is:

1. The firmware sets the data structures in memory.
2. The firmware programs the descriptors and the associated hardware.
3. The firmware sets the Start bit to initiate the transactions.
4. The hardware processes the descriptor, first setting the InProgress bit, and 

completes the transaction.

5. The hardware writes data back to memory (if any).
6. The hardware writes back the status to memory for the processed descriptor.
7. If no more descriptors are processed, the hardware clears the InProgress bit.

The assumption is an SMT firmware driver exists that understands the SMT hardware 

register interface and usage for sending and receiving SMBus messages.

1. The firmware allocates a 64B aligned buffer in memory to be used as the master 

descriptor ring buffer. Each descriptor is 16B long.

2. The firmware then programs up the MD Base Address (MDBA) register with the 

lower memory address of the descriptor ring buffer, and MD Size (MDS) register 

containing the number of descriptors in the ring.

3. The firmware initializes the FWmHeadPtr (MCTRL.FMHP) and HWmTailPtr 

(MSTS.HMTP) by writing all 0 into it.

4. The firmware also programs interrupts as needed.

The firmware schedules a master transaction in the descriptor ring buffer if the buffer is 

not full. The descriptor ring buffer is full if (FWmHeadPtr == HWmTailPtr - 1). The –1 

subtraction here needs to account for buffer utilization of N-1 for an N-deep buffer.