Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
353
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Register Maps
15.8.2
Registers in Memory Space
The SMT Controller registers in Memory Space are shown in
. These
Memory-Mapped I/O registers begin at the address specified by the 64-bit register
SMbus Base Address Register (SMTBAR) at offset 10h in the configuration space at
bus 0, devices 19 (decimal), function 0. The offset addresses are listed and must be
accessed by 32-bit memory transactions on the PC Express* interface or by local CPU.
Table 15-33. Memory Space Address and Description (Sheet 1 of 2)
Address Offset
Register Description and Name
General Registers
000h
General Control Register (GCTRL)
004h
Reserved
008h
SMT Interrupt Cause Location Register (SMTICL)
010h
Error Interrupt Mask Register (ERRINTMSK)
014h
Error AER Mask Register (ERRAERMSK)
018h
Error Status Register (ERRSTS)
01Ch
Error Information Register (ERRINFO)
020h - 0FCh
Reserved
Master Registers
100h
Master Descriptor Base Address Register (MDBA)
108h
Master Control Register (MCTRL)
10Ch
Master Status Register (MSTS)
110h
Master Descriptor Size Register (MDS)
114h
Retry Policy Register (RPOLICY)
118h - 1FCh
Reserved
Target Registers - General
200h
Target Buffer Base Address Register (TBBA)
208h
Target Control Register (TCTRL)
20Ch
Target Status Register (TSTS)
210h
Target Buffer Size Register (TBS)
214h
Reserved
218h
Hardware Target Head Pointer Register (HTHP)
21Ch
Firmware Target Tail Pointer Register (FTTP)
220h
Target Receive Control Register (TRxCTRL)
224h
Target Receive Status Register (TRxSTS)
228h
Target Address Control Register (TACTRL)
22Ch
Target Policy Register (TPOLICY)
230h - 23Ch
Reserved
Target Registers - Block Read
240h
General Purpose Block Read Control Register (GPBRCTRL)
244h
Generic Programmable Read Data Buffer Register (GPBRDBUF)
248h - 27Ch
Reserved