Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 2—SMBus 2.0 Unit 2 - PECI—C2000 Product Family
PECI Over SMBus
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
384
Order Number: 330061-002US
17.6.2
PECI Write-Read Protocol
The write-read protocol shown in
is the only protocol defined for messaging
between devices on the PECI. The write-read protocol allows an atomic operation that
first writes and then reads data between an originator and a target. Format of a write-
read message is given in
. The read and write Frame Check Sequence (FCS)
bytes are not calculated but may be required to have a byte allocated as part of the
specific command where described in
Legend:
Master to Slave
Slave to Master
Similar to
, the
PECI Message Header, the Address Timing Negotiation (NT) and Message Timing
Negotiation (MT) bits described in RS - Platform Environment Control Interface (PECI)
Specification, Revision 3.0 are not implemented. It is the responsibility of the BMC to
not include these timing bits in the header.
Figure 17-6. PECI Write-Read Protocol
8
Target Address
1 8
Write Length
8
Read Length
8
1
st
Data
(command)
N
M
8
2
nd
Data
8
...
8
N
th
Data
8
FCS
8
1
st
Data
8
...
8
M
th
Data
8
FCS