Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

389

This process provides the functions performed by the SMBus master (the BMC) and the 

SoC to trigger and complete a PECI Proxy command.

1. BMC performs an SMBus Block write transaction, formatted with the data 

associated with the requested PECI proxy command as shown in 

2. The SoC sets the CMD_BUSY bit in the Status byte and handles the requested PECI 

Command.

3. After completing the PECI operation, the SoC performs the following functions:

— Resets the CMD_BUSY bit in the Status byte.
— Sets the CMD_ERR bit if a PECI transaction error occurred; otherwise resets 

CMD_ERR bit.

— Sets the ERR_CODE byte with the End of Transaction condition.
— If the PECI transaction completed successfully, stores the PECI Response Data 

and transfers it to the BMC on the next Read command.

4. The BMC polls the Status Byte until the CMD_BUSY bit is cleared to indicate the 

completion of the command. If the PECI transaction completed successfully 

(CMD_ERR = ‘0’), the PECI Response data is valid.

In the case of an unsupported PECI command, the SoC responds with the appropriate 

error code.

In the case of an unsupported PECI command, the SoC responds with the appropriate 

error code.