Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

405

The RdEndPointConfig() command provides sideband read access to the PCI 

configuration space that resides within the processor, as well as the SSA sideband 

configuration space of each agent. The exact listing of supported devices, functions and 

registers is outside the scope of this document. PECI originators can access this space 

even before BIOS enumeration of the system busses. PECI originators may also 

conduct a device/function/register enumeration sweep of this space by issuing reads in 

the same manner that the BIOS would. 

 shows the RdEndPointConfig PECI 

Proxy Block Write format and 

 shows the RdEndPointConfig 

PECI Proxy Block Read format. 

The following Endpoints are accessible BUNIT (0x3), PUNIT (0x4), DUNIT0 (0x10), 

DUNIT1 (0x13), TUNIT (0x2).

Slave 

Address

(Write)

Write Address

SMBus 

Command

0x4C

BMC

Command 

Code

PECI Mode 

command code

0x62

Byte Count

N

Control Data

0x0B

Byte 1

SMBus-PECI 

Handshake 

Control

0x00

Value = 0x00 

No AW FCS Required

Byte 2

PECI Client 

Address

PECI 

Command

0x30

Byte 3

PECI Write 

Length

{0x07}

Byte 4

PECI Read Length

{0x02,

0x3,

0x5}

Byte 5

RdEndPointConfig

Command Code

0xC1

Use the same command for 

both, i.e., RdEndPointConfig 

is an alias.

Byte 6

Host ID and Retry

0x00

Byte 7

SoC Sideband 

Port

0x02
0x03
0x04
0x10
0x13

Sideband Port

• 0x02 = T-Unit
• 0x03 = B-Unit
• 0x04 = P-Unit
• 0x10 = D-Unit0
• 0x13 = D-Unit1

All other values return an 

Error.

Byte 8

Port Register 

Address Byte 1 

(LSB)

Any valid 

register 

address for 

the sideband 

port

Port offset
If the addressed sideband 

port register does not exist, 

an Error is returned.

Byte 9 

Port Register 

Address Byte 2

Byte 10

Port Register 

Address Byte 3

Byte 11

Port Register 

Address Byte 4 

(MSB)